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CY8CLEDAC01 ac/dc digital current-mode controller for led lighting cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134-1709 ? 408-943-2600 document number: 001-54122 rev. *b revised march 29, 2010 features ac offline input range from 80 to 277 vac constant current control with primary-side feedback energy star compliant for led lighting up to 30w output power range for universal inputs high efficiency (typically > 85%) tight led current regulation (typically < 2.5%) supports up to 130 khz switching frequency primary-side sensing eliminates opto-isolators quasi-resonant operation for highest efficiency and low emi no external compensation components required low startup current (typically 10 ?? a) built-in soft start multiple protection features ? current-sense resistor short protection (cssp) ? over-temperature protection (otp) ? output over-voltage protection (ovp) ? peak current limit protection (pclp) ? output short circuit protection (oscp) ? single-point fault protection applications ? offline led driver ? led replacement lamps ? led luminaires ? pre-regulator for intelligent dc-to-dc led controllers description the CY8CLEDAC01 is a digital current-mode controller incorpo- rating proprietary primary side control technology. this new technology eliminates the cost and complexity in traditional designs which use opto-isolated feedback and secondary-side regulation. the CY8CLEDAC01 uses an advance digital control algorithm to reduce system design time and improve reliabili ty. the control algorithm has cycle-by-cycle adap tive digital re gulation; this enables accurate secondary-si de constant-current operation without the need for secondary- side sense and control circuits. the cycle-by-cycle adaptive digita l regulation features fast dynamic response and tight output regulation using critical discontinuous conduction mode (cdcm) when driving led loads. the control algorithm for cycle-by-cycle regulation has internal compensation for g uaranteed system phase and gain margins; requiring no external components for loop compen- sation. the CY8CLEDAC01 has full featured circuit protection not normally available with other prim ary-side control solutions. the built-in protection features include over-voltage protection (ovp), output short circuit protection (oscp), peak current limit protection (pclp), and current-s ense resistor short protection (cssp), over-temperature protection (otp). the CY8CLEDAC01 also operates as a voltage-mode controller with all the current-mode controller features, allowing it to operate as a ac-to-dc front-end for intelligent led controllers such as cypress?s powerpsoc ? family. figure 1. simplified application diagram ac ac + _ ac input + + + ntc led 1 2 3 45 6 7 8 nc v sense v in sd vcc output i sense gnd optional power factor circuit isolated flyback conversion controller emi filter CY8CLEDAC01 +
CY8CLEDAC01 document number: 001-54122 rev. *b page 2 of 14 contents features ...........................................................................1 description ......................................................................1 contents ...........................................................................2 logic block diagram ...................................................3 functional descri ption ......... .............. .............. .........3 overview ........................................................................3 constant current operation ...........................................4 valley mode switching ........... .............. .............. ............4 protection features ........................................................4 understanding primary feedback ..................................5 constant voltage operation ...... .............. .............. .........6 dynamic load transient ................................................6 variable frequency operation .......................................6 internal loop compensation ..... .............. .............. .........6 pfm mode at light load ................................................6 pin information ..............................................................7 electrical specificat ions ..... .............. .............. ........8 absolute maximum ra tings ............................................8 electrical characteristics ... .............. ........... ........9 typical performance character istics ..... ..........10 ordering information .................................................12 ordering code definitions ........................................12 packaging information ............. .............. ........... ........13 physical package dimensions .......................................13 document history page ..............................................14 sales, solutions, and legal information ..........14 worldwide sales and design supp ort ............ ........... .....14
CY8CLEDAC01 document number: 001-54122 rev. *b page 3 of 14 logic block diagram figure 2. logic block diagram functional description overview the digital logic control block is the main block. all other blocks are inputs or outputs for the control block. the control block receives signals to determine the input voltage (v in ), output voltage (v sense ), temperature (sd), output operation (v cc ), and output current (i sense ). the control block has three output controls; sd mode (shutdown mode control), dac v ipk (current control), and v gate (gate drive control). the control block does not start operation until v cc has charged to the startup threshold (v ccst ) as shown in figure 3 . v cc is charged through a diode connection from v in . v in receives a voltage from a rectified main power input. when v cc is charged to v ccst , the startup block enables the v in scaling resistance (z vin ) and the control block. the startup block also monitors the v cc level and resets the system when v cc decreases to a brown-out level (v ccuvl ). the reset initiates a startup sequence where v cc is charged to v ccst level through a diode connection from v in . when the z vin resistor is enabled, a voltage v in_a is measurable by an adc. the output of the adc is provided to the control block for auto-calcula tion of the v in t on product where t on is the on time for the flyback mosfet. after the voltage on v in_a is above the startup low voltage threshold (v instlow ), the CY8CLEDAC01 commences an adaptive soft start function. the soft start control algorithm is applied at startup, during which the initial output pulses are small and gradually increase until the full pulse width is achieved. the v sense pin connects to the signal conditioning block. the signal conditioning block provides two inputs to the control block: v fb (voltage feed back) and v vms (voltage valley mode switch). v fb provides over-voltage protection and v cc measurement. v vms is the valley switch detection. v fb is monitored by the control block to determine if the output is over-voltage. when the control block detects an over-voltage condition, it enters a shutdown mode and wait for por to re-initialize the system. v vms is monitored by the control block to determine when the power in the flyback mosfet is at a minimum or in a 'valley'. the c ontrol block starts the next cycle at the 'valley' for maximum ef ficiency and minimum switching emi. - + - + adc - + dac 3 4 2 8 7 5 6 i peak v ipk 0 ~ 1v 1.1v 60kohm enable startup v in_a 0.2 ~ 2v z vin 5kohm digital logic control v in sd v sense v cc output i sense gnd signal conditioning v fb v vms i sd v sd-th gate driver v ocp r sd 8.33kohm sd mode v gate
CY8CLEDAC01 document number: 001-54122 rev. *b page 4 of 14 the sd pin connects to two blo cks; a switched current source (i sd ) and an analog comparator. these two blocks work together for otp and optional ovp. for an otp implementation, the sd pin can be connected to an external ntc component. the current source causes a voltage to be developed at the sd pin which causes the analog comparat or's output to be high or low depending upon a 1v comparat or reference. if the voltage across the ntc is less than 1v, the control block enters a shutdown mode and wait for po r to reinitialize the system. the i sense pin connects to circuitr y composed of three blocks: dac v ipk , i peak comparator, and v ocp comparator. these three blocks work together for soft-start control, peak current detection, and over-curr ent protection. the dac v ipk controls soft-start, minimizing stress asso ciated with system startup. the i peak comparator monitors the voltage at the i sense pin. the voltage is generated by current flowing through a small external resistor (r isense - not shown). when the i sense voltage reaches 1v, the i peak comparator asserts a high to the control block. the control block shuts off the output and waits for v vms detection; it then starts the next cycle. the v ocp comparator provides primary side over-current protection. when the voltage on i sense reaches 1.1v, the v ocp signal gets asserted. when over-current is detected, the control block enters a shutdown mode and waits for por to re initialize the system. the output pin connects to the gate driver block. the gate driver connects to the output pin that in turn connects to the flyback mosfet gate pin (not shown). the output pin is a digital control pin that switches between a high level (approxi- mately v cc ) and a low level (approximately ground). the duration for high (t on )and low (t off ) of the gate driver is a function of the control block operating upon its inputs: v in t on , v fb , v vms , sd, i peak , v ocp , and v cc . figure 3. device startup sequence constant current operation constant current (cc) mode is the normal operating mode for led lighting applications. CY8CLEDAC01 operates in cc mode when v sense is set below v sensenom . during this mode, the CY8CLEDAC01 regulates the output current at a constant level regardless of the output voltage. it operates in critical discon- tinuous conduction mode (cdcm) while in cc mode. to achieve cc regulation, the CY8CLEDAC01 senses the load current indirectly through the primary current. the primary current is detected by the i sense pin through a resistor from the mosfet source to ground. valley mode switching to reduce emi and switching losses in the mosfet, the CY8CLEDAC01 employs valley mode switching when operating in cdcm by switching at the lowest mosfet v ds (see figure 4 ). it detects valleys in the mosfet drain voltage indirectly through the v sense pin. this voltage is provided by the auxiliary winding of the flyback transformer and represents a copy of the secondary side characteristics (see figure 7 on page 6). figure 4. valley mode switching turning on at the lowest v ds generates lowest dv/dt; thus valley mode switching minimizes switching losses and reduces emi. to limit the switching frequency range, the CY8CLEDAC01 can skip valleys (second cycle in figure 4 ) when the switching frequency becomes too high. the CY8CLEDAC01 supports valley mode switching in both cc and constant voltage (cv) mode s of operation. this feature is superior to other quasi-resonant technologies which only support valley mode switching during constant voltage operation. protection features the CY8CLEDAC01 has full feat ured circuit protection not normally available with other primary-side control solutions. the built-in protection features include over-voltage protection (ovp), output short circuit protection (oscp), peak current limit protection (pclp), and current-s ense resistor short protection (cssp), over-temperature protection (otp). in an event a protection is triggered, v cc discharges below v ccuvl and causes a por except in case of pclp. the controller now in itiates a new soft start cycle and continues to attempt start-up. it is unable to start up until the fault condition is removed. current sense resistor short protection (cssp) if the i sense sense resistor is shorted, there is a potential danger of an over-current condition not being detected. the CY8CLEDAC01 has a separate circuit to detect this fault. this protection mode is triggered if the i sense voltage is below 0.15v in cc mode and only at heavy loads in cv mode. over-temperature protection (otp ) and/or output over-voltage protection (ovp) the shutdown (sd) pin along with an external ntc provides over-temperature protection. the sd pin also provides optional over-voltage protection by sensing a scaled auxiliary winding
CY8CLEDAC01 document number: 001-54122 rev. *b page 5 of 14 voltage from the flyback transformer using external components. the CY8CLEDAC01 switches between monitoring an over-temperature fault and an over-voltage fault on the sd pin by using the sd mode control signal (shown in figure 2 on page 3). for an over-temperature fault the voltage on the ntc is detected by connecting an internal current source to the pin. for an over-voltage fault the voltage on the sd pin is checked using an internal pulldown resistance r sd . the measurements are made during the last v gate cycle in the meas urement window to allow transients to settle.(shown in figure 5 ) figure 5. sd detection when sd mode is high and the voltage across the ntc is lower than 1v during normal operation or 1.2v during start-up an otp is triggered. when sd mode is low and the sensed voltage on the sd pin is higher than 1v an ovp fault is triggered. output over-voltage protection (ovp) the CY8CLEDAC01 includes a functi on that protects against an output over-voltage. the output voltage is monitored by the v sense pin. the protection is trigger ed if the voltage at this pin exceeds the over-voltage threshold v sensemax . peak current limit protection (pclp) the i sense pin of the CY8CLEDAC01 monitors the primary peak current. this enables cycle-by-cycle peak current control and limiting. when the primary peak current multiplied by the sense resistor value is greater than 1.1v, an over-current condition is detected and the ic immediately turns off the mosfet driver. during the next switching cycle, the driver sends out a regular switching pulse and turns off again if the ocp threshold is still reached. normal switching resumes if the fault is removed and the ocp threshold is not reached. output short circuit protection (oscp) the CY8CLEDAC01 includes a functi on that protects against an output short circuit. the output voltage is monitored by the v sense pin. the protection is trigger ed if the voltage at this pin is below 0.22v. note when the v sense is at this level, the controller is by default operating in cc mode and hence an over current condition cannot happen. single point fault protection the CY8CLEDAC01 detect a short on any of the following pins i sense , v sense , v cc , output, and sd. therefore, any single point fault is protected against. understanding primary feedback figure 6 illustrates a simplified flyback converter. when the switch q1 conducts during t on (t) , the current i g (t) is directly drawn from rectified sinusoid v g (t) . the energy e g (t) is stored in the magnetizing inductance l p . the rectifying diode d1 is reverse biased and the load current i o is supplied by the secondary capacitor c o . when q1 turns off, d1 conducts and the stored energy e g (t) is delivered to the output. figure 6. simplified flyback converter when operating in cc mode, to tightly regulate output current, information about the load current needs to be accurately sensed. to achieve cc regulation, this information can be derived indirectly by sensing the primary current. when operating in cv mode, to tightly regulate output voltage, information about the output voltage and load current needs to be accurately sensed. in the dcm flyback converter, this infor- mation can be read through the auxiliary winding. during the q1 on time, the load current is supplied from the output filter capacitor c o . the voltage across l p is v g (t) , assuming the voltage dropped across q1 is zero. the current in q1 ramps up linearly at a rate of: equation 1 at the end of on time, the cu rrent has ramped up to: equation 2 this current represents a stored energy of: equation 3 when q1 turns off, i g (t) in l p forces a reversal of polarities on all windings. ignoring the commutation time caused by the leakage inductance l kp at the instant of turn-off, the primary current transfers to the secondary at a peak amplitude of: equation 4 assuming the secondary winding is master and the auxiliary winding is slave, the auxiliary voltage is given by: v gate sd mode ovp detection otp detection connected to r sd connected to i sd v in (t) ac ac + _ + i in (t) v g (t) i g (t) i d (t) i o v o c o d1 t s (t) q1 l p n p l s n s l aux n aux p g g l t v dt t di ) ( ) ( ? p on g peak g l t t v t i ? ? ) ( ) ( _ 2 _ ) ( 2 t i l e peak g p g ? ? t i n n t i peak g s p d ? ?
CY8CLEDAC01 document number: 001-54122 rev. *b page 6 of 14 equation 5 and reflects the output voltage as shown in figure 7 . figure 7. auxiliary voltage waveforms the voltage at the load differs from the secondary voltage by a diode drop and ir losses. the diode drop is a function of current, as are ir losses. thus, if the secondary voltage is always read at a constant secondary current, the difference between the output voltage and the secondary voltage is a fixed ? v. further, if the voltage can be read when the secondary current is small; for example, at the knee of the auxiliary waveform (see figure 7 ), then ? v is also small. with the CY8CLEDAC01, ? v can be ignored. the real time waveform analyzer in the CY8CLEDAC01 reads the auxiliary waveform informati on cycle by cycle. the part then generates a feedback voltage v fb . the v fb signal precisely represents the output voltage and is used to regulate the output voltage. constant voltage operation the CY8CLEDAC01 also features a constant voltage (cv) mode. it operates in cv mode when v sense is set between v sensenom and v sensemax . after soft start is completed, the digital control block measures th e output conditions. it deter- mines output power levels and adjusts the control system according to a light load or a heavy load. it uses cdcm or pulse width modulation (pwm) at high output power levels and switches to pulse frequency modulation (pfm) at light loads to minimize power dissipation. the pwm switching frequency is between 30 khz and 130 khz, depending on the line and load conditions. dynamic load transient there are two components that compose the voltage drop during a load transient event. v drop(sense) is the drop in voltage before the v sense signal is able to show a significant drop in output voltage. this is deter- mined by v min or the reference voltage at which a load transient is detected. the smaller the v min is, the smaller is the drop in voltage. equation 6 remember that a smaller v min is less tolerant of noise and can lead to signal distortion in v sense . the final drop in voltage is due to the time from when v sense drops v min to when the next v sense signal appears. in the worst case condition this is how much voltage drops during the longest switching period. equation 7 a larger output capacitance in this case greatly reduces the v drop(ic) . variable frequency operation an internal circuit checks for the falling edge of v sense on every switching cycle. if th e falling edge of v sense is not detected, the off-time is extended until the falling edge of v sense is detected. the maximum allowed transf ormer reset time for the CY8CLEDAC01 is 75 s. internal loop compensation the CY8CLEDAC01 incorporates an internal digital error amplifier with no requirement fo r external loop compensation. for a typical power supply design, the loop stability is guaranteed to provide at least 45 degrees of phase margin and -20 db of gain margin. pfm mode at light load the CY8CLEDAC01 normally operates in a fixed frequency pwm or critical discontinuous conduction mode when i out is greater than approximately 10 per cent of the specified maximum load current. as the output load i out is reduced, the on-time t on is decreased. the moment the load current drops below 10 percent of nominal, the controller transitions to pulse frequency modulation (pfm) mode. thereafter, the on-time is modulated by the line voltage and the off-time is modulated by the load current. the device automatically returns to pwm mode when the load current increases. ) v ( ? ? ? o s aux aux v n n v ?? () () () (min) () out design drop sense sense nom sense sense nom v vvv v ??? ) ( ) ( ? ?
CY8CLEDAC01 document number: 001-54122 rev. *b page 7 of 14 pin information pin no. name type description 1 nc - no connection 2 v sense analog input sense signal input from auxiliary winding. this provides the secondary voltage feedback used for output regulation. 3 v in analog input sense signal input from the rectified line voltage. v in is used for line regulation. the input line voltage is scaled down using a resistor network, and is used for input under-voltage and over-voltage protection. th is pin also provides the supply current to the ic during startup. 4 sd analog input external shutdown control. this pin should be pulled down to gnd using a 20k ? resistor if shutdown control is not required. 5 gnd ground ground 6 i sense analog input primary current sense. used for cy cle by cycle peak current control. 7 output output gate drive for external mosfet switch 8 v cc power input power supply for the controller during norma l operation. the controller starts up when v cc reaches 12v (typical) and shuts down when the v cc voltage is below 6v (typical). a decoupling capacitor should be connected between the v cc pin and gnd.
CY8CLEDAC01 document number: 001-54122 rev. *b page 8 of 14 electrical specifications this section presents the dc and ac electrical specifications of the CY8CLEDAC01, of the powe rpsoc device family. for the most up to date electrical specifications, confirm that yo u have the most recent data sheet by going to the web at http://www.cypre ss.com/powerpsoc . specifications are valid for -40c ? t a ? 85c and t j ? 125c, except where noted. ta b l e 1 lists the units of measur e that are used in this section. absolute maximum ratings exceeding maximum ratings may shorten the useful life of the device. not all user guidelines are production tested table 1. units of measure symbol unit of measure symbol unit of measure symbol unit of measure c degrees celsius kbit 1024 bits ma milliampere db decibels khz kilohertz ms millisecond hz hertz k ? kilohms mv millivolts pp peak-to-peak mhz megahertz ma milliwatts ? sigma:one standard deviation m ? megaohms na nanoamperes v volts ? a microamperes ns nanoseconds ? ohms ? f microfarads nv nanovolts kb 1024 bytes ? h microhenrys pa picoamperes ppm parts per million ? s microseconds pf picofarads sps samples per second ? v microvolts ps picoseconds w watts ? vrms microvolts root-mean-square ff femtofarads a amperes ? w microwatts symbol description min typ max units notes v cc dc supply voltage range -0.3 - 18 v pin 8, i cc = 20 ma max i cc dc supply current at v cc pin - - 20 ma pin 8 output pin voltage -0.3 - 18 v pin 7 v sense pin voltage -0.7 - 4.0 v pin 2, i sense < 10 ma v in pin voltage -0.3 - 18 v pin 3 i sense pin voltage -0.3 - 4.0 v pin 6 sd pin voltage -0.3 - 18 v pin 4 p d power dissipation - - 526 mw t a < 25c t j,max maximum junction temperature - - 125 c t stg storage temperature -65 - 150 c t lead lead temperature - - 260 c during ir reflow for < 15 seconds ? ja thermal resistance junction-to-ambient - - 160 c/w v esd esd voltage rating - - 2000 v as per jedec jesd22-a114 i lu latch up current -100 - 100 ma as per jedec jesd78
CY8CLEDAC01 document number: 001-54122 rev. *b page 9 of 14 electrical characteristics notes 1. adjust v cc above the startup threshold before setting at 12v. 2. these parameters are not 100% tested , guaranteed by design and characterization. 3. operating frequency varies based on the line and load conditions, see functional description on page 3 for more details. v cc =12v; -40c ? t a ? 85c unless otherwise specified [1] symbol description min typ max units notes v in section (pin 3) v instlow startup low voltage threshold 335 369 406 mv t a = 25c positive edge i inst startup current - 10 15 ? av in = 10v, c v cc =10 ? f z in input impedance - 5 - k ? after startup v sense section (pin 2) i bvs input leakage current - - 1 ? a vsense = 2v v sensenom nominal voltage threshold 1.523 1.538 1.553 v t a = 25c negative edge v sensemax output ovp threshold 1.790 1.846 1.900 v t a = 25c negative edge output section (pin 7) r ds(on)lo output low level on-resistance - 40 - ? i sink = 5 ma r ds(on)-hp output high leve l on-resistance - 102 - ? i source = 5 ma t r rise time [2] - 200 300 ns t a = 25c; cl = 330 pf; 10% to 90% t f fall time [2] -4060nst a = 25c; cl=330 pf; 10% to 90% f swmax maximum switching frequency [3] - 130 140 khz any combination of line and loads v cc section (pin 8) v ccmax maximum operating voltage - - 16 v v ccst startup threshold 10.8 12 13.2 v v cc rising v ccuvl under-voltage lockout threshold 5.5 6.0 6.6 v v cc falling i cc operating current - 3.5 - ma c l = 330 pf; v sense = 1.5v i sense section (pin 6) v peak peak limit threshold 1.1 v v rsns i sense short protection reference - 0.15 - v v regth cc regulation threshold limit - 1.0 - v sd section (pin 4) v sdth shutdown threshold 0.95 1.0 1.05 v v sdthst shutdown threshold in startup - 1.2 - v i bvsd input leakage current - - 1.0 ? av sd = 1.0v r sd pull down resistance 7.916 8.333 8.750 k ? i sd pull up current source 96 107 118 ? a
CY8CLEDAC01 document number: 001-54122 rev. *b page 10 of 14 typical performance characteristics figure 8. v cc supply current versus v cc figure 9. switching frequency% change versus temperature figure 10. startup threshold versus temperature figure 11. internal reference versus temperature
CY8CLEDAC01 document number: 001-54122 rev. *b page 11 of 14 figure 12. t on compensation chart note 4. ? i out refers to the difference in constant current limit between 264 vac and 90 vac when no r dly and c dly are applied.
CY8CLEDAC01 document number: 001-54122 rev. *b page 12 of 14 ordering information ordering code definitions ordering code no. of pins package temperature range CY8CLEDAC01 8 soic -40c to 85c cy 8 c led ac 01 01 = non dimmable ac = offline family code: led = led applications technology code: c = cmos marketing code: 8 = powerpsoc family company id: cy = cypress
CY8CLEDAC01 document number: 001-54122 rev. *b page 13 of 14 packaging information physical package dimensions figure 13. 8-pin small outline (soic) package 001-54263 **
document number: 001-54122 rev. *b revised march 29, 2010 page 14 of 14 powerpsoc? and psoc? are registered trademarks and psoc designer? is a trademark of cypress semiconductor corp. all other trade marks or registered trademarks referenced herein are property of the respective corporations. CY8CLEDAC01 ? cypress semiconductor corporation, 2009. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturers? representative s, and distributors. to find t he office closest to you, visit us at cypress locations. products automotive clocks & buffers interface lighting & power control memory optical & image sensing psoc touch sensing usb controllers wireless/rf psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: CY8CLEDAC01 ac/dc digital current-mode controll er for led lighting document number: 001-54122 revision ecn no. orig. of change submission date description of change ** 2721319 kjv/aesa 06/19/2009 new data sheet *a 2829351 kjv/pyrs 12/16/2009 added contents . updated text in features , description , and functional description sections. updated electrical specifications *b 2901104 kjv/ved 03/29/2010 release to web.

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